%0 Journal Article
%A DING Hao-yu
%A LIU Ma-liang
%A LUO Ze-yong
%A YANG Yin-tang
%A ZHU Zhang-ming
%T 1.6 Gbit/s Synchronization Circuit for High Speed Digital-to-Analog Converters
%D 2014
%R 10.13190/j.jbupt.2014.04.015
%J Journal of Beijing University of Posts and Telecommunications
%P 69-73
%V 37
%N 4
%X <p>A new synchronization circuit was proposed. Due to requirement of the GHz sampling D/A converter, the circuit employs high-speed dynamic comparators and flip-flops to receive the input data from the low voltage differential signaling (LVDS) interface, which has the advantage of low power and low complexity. At the same time, this circuit adopts a low jitter analog delay locked loop and digital phase detector to obtain the proper synchronous clock, thereby, the clock frequency range of the synchronous circuit can be improved. Based upon the SMIC 0.18 um 1.8 V CMOS process, the simulation gives that the clock frequency of the synchronization circuit is within the range of 250~800 MHz, and the data rate is 500 Mbps~1.6 Gbps. The circuit can be used in the synchronization of the GHz sampling DAC core and the external LVDS transmitter interface.</p>
%U https://journal.bupt.edu.cn/EN/10.13190/j.jbupt.2014.04.015