%0 Journal Article
%A JIANG Lin
%A SHAN Rui
%A SHEN Xu-bang
%A SONG Hui
%A ZHU Yun
%T Design of Distributed Shared Memory Structure for Array Processor
%D 2017
%R 10.13190/j.jbupt.2017.04.002
%J Journal of Beijing University of Posts and Telecommunications
%P 9-15
%V 40
%N 4
%X With the increasing of number of processors, the problem of memory wall was more severely. In order to alleviate this problem, two-level mixed interconnection network was proposed: fast crossbar for local data transfer and network on chip for long distance data communication. Meanwhile data transfer mechanism was designed to support unified addressing. Two memory architecture sizes were implemented on field rpogrammable gate array, and area, frequency and power consumption were evaluated. A mixed simulation testbench based on SystemC language was developed. The simulation results show that the designed architecture has higher memory access bandwidth and lower local accessing latency.
%U https://journal.bupt.edu.cn/EN/10.13190/j.jbupt.2017.04.002