%0 Journal Article
%A LI Yang
%A LIU Bin
%A WU Hao
%A ZHANG Chu-wen
%T The Hardware Measurement System for High-Speed Network Flow
%D 2017
%R 10.13190/j.jbupt.2017.s.006
%J Journal of Beijing University of Posts and Telecommunications
%P 24-28
%V 40
%N s1
%X Aiming at the problem that how to trade off the access throughput, accuracy and capacity of counter memory in high-speed network measurement, the non-linear sampling was adopted to develop an FPGA-based network measurement system FPGA-based adaptive sampling measurement (FAST). The key designs of FAST include the centralized state machine, the separate function banks in counter memory and the parallel export operations. Through numerous evaluations, this FAST prototype can adaptively tune sampling rate according to real-time flow volume and reach a high counter compression rate with more than 99% average accuracy rate. The throughput attains to 27.4Mpps.
%U https://journal.bupt.edu.cn/EN/10.13190/j.jbupt.2017.s.006